Highly Concurrent VLSI Computing Structures for DCA

In this paper highly concurrent pipelined computing structures based on a constrained digital contour smoothing are described. The smoothing minimizes the undersampling, digitizing and quantizing error and so it is able to improve the stability of invariants calculation. The word-level and bit-level systolic arrays for completely pipelined calculation of the constrained least-squares digital contour smoothing are described. They represent the heart of the concurrent pipelined VLSI computing structures which enable to calculate invariants, such as the length, the area, the moment invariants and to perform the smoothed contour encoding, in parallel. The computing structures achieve very high throughputs and can be realized on a single VLSI chip. They can be used for purposes of real-time digital curves analysis. Key-Words: Digital curves analysis, digital contour smoothing, circulant Toeplitz matrices, bitlevel systolic arrays, pipelined architectures, VLSI